Flash memory is a common type of non-volatile semiconductor memory device. Non-volatile refers to the trait of retaining stored data when power is turned off. Because Flash memory is non-volatile, it is commonly used in power conscious applications, such as in battery powered cellular phones, personal digital assistants (PDAs), and in portable mass storage devices such as memory sticks.
Flash memory devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, a Flash memory may include one or more high density core regions and a low density peripheral portion formed on a single substrate. The high density core regions typically include arrays of individually addressable, substantially identical floating-gate type memory cells. The low density peripheral portion may include input/output (I/O) circuitry, circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing), and voltage regulation and supply circuitry.
In one particular type of Flash memory architecture, called NOR Flash memory, memory cells within the core portion are coupled together in a circuit configuration in which each memory cell has a drain, a source, and a stacked gate. In operation, memory cells may be addressed by circuitry in the peripheral portion to perform functions such as reading, erasing, and programming of the memory cells.
When programming and erasing NOR-type Flash memory cells, multiple memory cells may be programmed at once. In a programming operation, each cell being programmed acts as a load to the power generation and supply circuitry in the memory device. Ideally, the power generation and supply circuitry should provide a stable and consistent output power supply to the memory cells.
A voltage regulator circuit may be used to help stabilize power supplied to the memory cells during programming, reading, or erasing of the memory cells. FIG. 1 is a diagram illustrating one existing implementation of a voltage regulator.
As shown in FIG. 1, a voltage regulator 100 includes a two-stage operational-amplifier (op-amp) section 110, a load capacitor C1, and a resistor R. C1 and R are connected in parallel and to the output of op-amp section 110. Op-amp section 110 includes an op-amp 115 connected as a differential amplifier that outputs a signal to a unity gain op-amp 120. Power lines, not shown, may also be connected op-amps 115 and 120. The positive terminal of op-amp 115 is connected to Vref, which is set to a reference voltage that is desired at the output of the voltage regulator (Vout). The negative terminal of op-amp 115 receives feedback from Vout. Capacitor Cc is connected between the output and input of unity gain op-amp 120.
In operation, the feedback path from Vout to the negative terminal of op-amp 115 tends to stabilize Vout to output a voltage equal to Vref. C1 may be a relatively large capacitor that is used to compensate for load variations in the circuitry connected to Vout. For example, if the load increases to temporarily draw more current than can be supplied from the output of op-amp 120, C1 may temporarily make up the difference.
In situations in which the load seen by voltage regulator 100 changes quickly and/or significantly, Vout may exhibit relatively large overshoot and long settling times. This can negatively impact the circuitry that draws power from Vout. For example, in the situation where this circuitry is an array of flash memory cells, relatively large overshoot and long settling times can negatively impact the programming, erasing, or reading speed of the memory cells. Accordingly, it is desirable to minimize the overshoot and/or settling time of the voltage regulator.